Projects

This project designs and implements a 1x3 Router using Verilog HDL, integrating crucial components like FSM, sync modules, FIFO buffers, and regs for efficient data routing. Tools like Synopsys Spyglass ensure error-free RTL code, followed by synthesis using Xilinx Vivado and Synopsys DC for optimal hardware implementations. Demonstrating the importance of sophisticated tools in HDL-based design, it's implemented on the Basys 3 FPGA Board.

Explore the power of simplicity with our Single core RISC-V tailored for I-Type Instructions. This project, inspired by the foundational RISC-V architecture, boasts a streamlined design optimized for efficiency and speed in executing I-Type instructions. By focusing on a single cycle per instruction, our processor ensures swift and precise execution, making it an ideal choice for tasks demanding rapid processing of immediate operand instructions.

A register file is a digital storage element in a computer's central processing unit (CPU) that stores data temporarily. It consists of a set of registers, each capable of storing a binary value. In a dynamic register file, the term "dynamic" typically implies that the register file can be reconfigured or modified.

A Linear Feedback Shift Register (LFSR) is a type of shift register that uses linear feedback to generate pseudo-random sequences. It is commonly employed in digital circuit design, cryptography, and error detection/correction applications. Verilog, a hardware description language (HDL), is often used to model and simulate digital circuits.